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发明名称
延缓打线通道内下模流之半导体封装构造
摘要
一种延缓打线通道内下模流之半导体封装构造,主要包含一具有打线通道之基板、一晶片、一缩口元件以及一模封胶体。该晶片系设置于该基板上并局部覆盖该打线通道而使该打线通道两端露出以形成有一入胶口与一出胶口。该缩口元件系设置于该基板并局部遮盖该入胶口,以缩小该入胶口。该模封胶体系具有一在基板上之上模封部与一在该打线通道内之下模封部。藉此,形成该上模封部与该下模封部之模流速度能达到平衡,可解决知上模封部填胶空隙与下模封部在基板底部溢胶之问题。
申请公布号
TWI360849
申请公布日期
2012.03.21
申请号
TW096141933
申请日期
2007.11.06
申请人
华东科技股份有限公司 高雄市高雄加工出口区北一路18号
发明人
李国源;赵匡祺;陈政泰
分类号
H01L21/56;H01L23/28
主分类号
H01L21/56
代理机构
代理人
许庆祥 高雄市苓雅区新光路24巷31号
主权项
地址
高雄市高雄加工出口区北一路18号
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