TWO-TERMINAL TRANSISTOR MEMORY UTILIZING EMITTER-BASE AVALANCHE BREAKDOWN

摘要

A semiconductor memory cell containing a single transistor having an uncontacted base is operated as a two-terminal device with a voltage pulse circuit coupled to the collector and a conduction detector circuit coupled to the emitter. Bit information is written into the cell by setting the potential of the base to one of two values, which represent respectively a "1" and a "0." A "1" is written into the cell by applying a negative polarity voltage pulse to the collector of sufficient amplitude to forward bias the collector-base junction and to bias the emitter-base junction to avalanche breakdown. To read out information previously stored in the cell and to write a "0" into the cell, a positive going voltage pulse is applied to the collector.