发明名称 |
Method and system for rapidly identifying silicon manufacturing defects |
摘要 |
The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first retrieve information about an electrical failure from an IC's electrical test result and then identify a set of electrical elements from the IC's layout design including a start resource and an end resource. Next, the method and system identify a physical signal path between the start resource and the end resource using the IC's layout design. Finally, the method and system examine a corresponding region on the semiconductor die that covers the physical signal path for manufacturing defects that may be responsible for the electrical failure. |
申请公布号 |
US8141026(B1) |
申请公布日期 |
2012.03.20 |
申请号 |
US20080138080 |
申请日期 |
2008.06.12 |
申请人 |
REILLY DANIEL L.;CAO PHONG T.;ALTERA CORPORATION |
发明人 |
REILLY DANIEL L.;CAO PHONG T. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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