| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress phase distortion of a multi-phase clock signal, in a receiving circuit that receives data using the multi-phase clock signal. <P>SOLUTION: A receiving circuit 30 has: a phase interpolator 40 that generates a multi-phase clock output signal having an arbitrary phase from a multi-phase clock input signal, based on a phase code; a phase fluctuation circuit 52 that gives fluctuation to the phase code; a phase detection circuit 46 that detects fluctuation of the multi-phase clock output signal to the fluctuation of the phase code; a distortion estimation circuit 52 that estimates phase distortion of the phase interpolator 40, based on a detection result of the phase detection circuit 46; and a correction circuit 52 that corrects the phase distortion, based on an estimation result of the distortion estimation circuit 52. <P>COPYRIGHT: (C)2012,JPO&INPIT |
