PLL FREQUENCY SYNTHESIZER

摘要

In a digital PLL frequency synthesizer (101), by switching from a first oscillation signal phase information (Rv[k]) after lock detection to a second oscillation signal phase information (Rv_est[k]) estimated by an estimating unit (20) on the basis of a previous oscillation signal phase information and a phase difference, the first oscillation signal phase information carrying the risk of having an error in an ordinary state (locked state) is not used, and also a latch circuit that performs a high-speed operation for conventional re-clocking is not required. Accordingly, deterioration of phase noise characteristics is avoided, and power consumption is reduced compared to the conventional art.