Power MOS device

摘要

The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.