发明名称 Adder with reduced capacitance
摘要 An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.
申请公布号 US8135768(B2) 申请公布日期 2012.03.13
申请号 US20060364915 申请日期 2006.03.01
申请人 STEWART MALCOLM;MTEKVISION CO., LTD. 发明人 STEWART MALCOLM
分类号 G06F7/50 主分类号 G06F7/50
代理机构 代理人
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