发明名称 |
Method and apparatus for correcting phase offset errors in a communication device |
摘要 |
A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An auto-tuning circuit and technique provide a measurement of static phase error by integrating the static phase error in the DLL/PLL circuit. A correction value is determined and applied as a current at the charge pump or as a time/phase offset at the phase detector to minimize static phase error. During normal operation the DLL/PLL is operated with the correction value resulting in substantially reduced spur levels and/or improved settling time. |
申请公布号 |
US8134393(B1) |
申请公布日期 |
2012.03.13 |
申请号 |
US20100893266 |
申请日期 |
2010.09.29 |
申请人 |
NAGARAJ GEETHA B.;HARRINGTON THOMAS R.;SALVI RAUL;MOTOROLA SOLUTIONS, INC. |
发明人 |
NAGARAJ GEETHA B.;HARRINGTON THOMAS R.;SALVI RAUL |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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