发明名称 |
Method for testing noise immunity of an integrated circuit and a device having noise immunity testing capabilities |
摘要 |
A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit. |
申请公布号 |
US8134384(B2) |
申请公布日期 |
2012.03.13 |
申请号 |
US20090514005 |
申请日期 |
2009.05.07 |
申请人 |
WEIZMAN YOAV;FEFER YEHIM-HAIM;SOFER SERGEY;FREESCALE SEMICONDUCTOR, INC. |
发明人 |
WEIZMAN YOAV;FEFER YEHIM-HAIM;SOFER SERGEY |
分类号 |
G01R31/34 |
主分类号 |
G01R31/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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