发明名称 |
Drive circuit for generating a delay drive signal |
摘要 |
A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval. |
申请公布号 |
US8134525(B2) |
申请公布日期 |
2012.03.13 |
申请号 |
US20070734311 |
申请日期 |
2007.04.12 |
申请人 |
YANG CHIH-HSIANG;TU MING-HUNG;CHANG KE-CHIH;AU OPTRONICS CORPORATION |
发明人 |
YANG CHIH-HSIANG;TU MING-HUNG;CHANG KE-CHIH |
分类号 |
G09G3/36 |
主分类号 |
G09G3/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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