发明名称 CONVERTITORE DI LIVELLO LOGICO
摘要 <p>A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the flip-flop arrangement. The forcing circuitry has an input terminal to receive a logic input signal having a given level to produce switching of the flip-flop arrangement and generate at the output line(s) of the flip-flop arrangement, a logic output signal(s) whose voltage level is converted with respect to the level of the logic input signal. The converter includes, interposed between each of the two first electronic switches in the flip-flop arrangement and a respective one of the second electronic switches in the forcing circuitry, at least one respective cascode electronic switch to limit the voltage across the two first electronic switches in the flip-flop arrangement.</p>
申请公布号 IT1392565(B1) 申请公布日期 2012.03.09
申请号 IT2008TO00977 申请日期 2008.12.23
申请人 STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. 发明人 JERABEK TOMAS;NAPRAVNIK KAREL
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