| 摘要 |
A digital multiplier for multiplying together two binary numbers includes a linear array of bit processing cells. Each cell has two input connections (Ia, Ib) to which are applied successive bits of the two numbers, and two output connections (Oa, Ob) by means of which the successive bits are applied to the next cell. Each cell also includes multiplying means (G) for multiplying together one bit of each number, and an adder (AD) operable to add together and store the results of successive multiplication operations. <IMAGE> |
