| 摘要 |
<p>PURPOSE:To reduce the clock skew of the entire system employing many circuits by providing a variable delay type clock input buffer whose delay quantity is controlled in response to a control data. CONSTITUTION:An external clock input is given to a master clock input buffer 3 in an LSI chip having plural blocks 2..., and then to variable delay type clock input buffers 4... of each logic block 2 from the input buffer 3 in common. Then, e.g., serial input type shift registers 5... to provide a delay quantity control data are provided corresponding to the variable delay type clock input buffers 4... and a control data inputted from the outside of the LSI is set to the shift registers 5.... Thus, the clock skew of the entire system is reduced by properly adjusting the delay quantity of the variable delay type clock input buffers 4 of each LSI respectively.</p> |
