发明名称 |
Semiconductor memory device using only single-channel transistor to apply voltage to selected word line |
摘要 |
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.
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申请公布号 |
US8130589(B2) |
申请公布日期 |
2012.03.06 |
申请号 |
US201113109694 |
申请日期 |
2011.05.17 |
申请人 |
NAKAMURA HIROSHI;IMAMIYA KENICHI;KABUSHIKI KAISHA TOSHIBA |
发明人 |
NAKAMURA HIROSHI;IMAMIYA KENICHI |
分类号 |
G11C8/00;G11C11/413;G11C16/04;G11C16/06;G11C16/08;H01L27/115 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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