发明名称 |
Closed-loop 1×N VLSI design system |
摘要 |
Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite. |
申请公布号 |
US8132134(B2) |
申请公布日期 |
2012.03.06 |
申请号 |
US20080200076 |
申请日期 |
2008.08.28 |
申请人 |
CORREALE, JR. ANTHONY;BAKER MATTHEW W.;BOWERS BENJAMIN J.;RASHID IRFAN;STEINMETZ PAUL M.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CORREALE, JR. ANTHONY;BAKER MATTHEW W.;BOWERS BENJAMIN J.;RASHID IRFAN;STEINMETZ PAUL M. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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