| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress increase in a memory cell area, which is caused by a restriction in gate wiring by a leakage current and a restriction of design rules, in a memory cell including a CMOS inverter. <P>SOLUTION: A first wire FL1 and a second wire FL2 are arranged as a first metal layer of a memory cell 1A including a first inverter IV1 and a second inverter IV2. The first wire FL1 is connected to two drains D of the first inverter IV1 and a second gate wire GL2 of the second inverter IV2. The second wire FL2 is connected to two drains D of the second inverter IV2 and a first gate wire GL1 of the first inverter IV1. The first wire FL1 and the second wire FL2 are arranged so as to be superposed with the second gate wire GL2 and the first gate wire GL1, respectively. On a layer higher than the first metal layer, a second metal layer and a third metal layer higher than the second metal layer are arranged. <P>COPYRIGHT: (C)2012,JPO&INPIT |
