发明名称 DECISION FEEDBACK EQUALIZER, RECEIVING CIRCUIT, AND DECISION FEEDBACK EQUALIZATION PROCESSING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a decision feedback equalizer which can process parallel data of the number L at high speed. <P>SOLUTION: A decision feedback equalizer comprises: a circuit for performing equalization calculation in relation to input data of an target sample and seeking a calculation value of the number M concerning each combination of the plural number M which a data decision value can have in relation to the input data of samples before the target sample; equalization calculation circuits of the number L for performing equalization calculation in parallel on the different input data of the samples of the number L in a chronological order; a logical circuit for generating logical values of the number M by selecting and arranging some of the calculation values of the number M in relation to one sample out of the samples of the number L according to the calculation values of the number M in relation to the sample right before a sample; a selection circuit for selecting one of the logical values of the number M according to the data decision value in relation to the input data of the samples before the sample right before and for outputting it as the data decision value in relation to the input data of the one sample. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012039267(A) 申请公布日期 2012.02.23
申请号 JP20100175743 申请日期 2010.08.04
申请人 FUJITSU LTD 发明人
分类号 H04B3/06 主分类号 H04B3/06
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