发明名称 Maximum likelihood decoder and decoding method
摘要 A signal vector sequence corresponding to one block which is inputted in continuous n symbol sections is held in a vector sequence holding portion 11. A virtual information generating portion 12 and a coding portion 13 successively generate, with respect to N paths which can exist in the one block, corresponding virtual code vector sequences. A metric calculating portion 14 receives the signal vector sequence held in the vector sequence holding portion 11 and each of the virtual code vector sequences applied from the coding portion 13 to calculate respective metrics of the N paths. A metric comparing portion 16 and a metric holding portion 15 judge a maximum likelihood path having the minimum metric on the basis of the respective metrics calculated by the metric operating portion 14. When processing of the N paths is terminated, an information holding portion 17 acquires from the virtual information generating portion 12 as it existed before the coding on the virtual code vector sequence corresponding to the maximum likelihood path and outputs the information as the result of the decoding. In calculating the respective metrics of the N paths which can exist in one block, the metric calculating portion 14 finds a metric value in a state where the terms of the square of the magnitude of a signal vector are previously subtracted from each of calculation expressions. Consequently, the calculation processing is simplified, and the circuit arrangement is simplified.
申请公布号 US5608737(A) 申请公布日期 1997.03.04
申请号 US19950391002 申请日期 1995.02.21
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 KIMURA, TOMOHIRO;HARADA, YASUO;OHTA, KAZUHIRO
分类号 H03M13/41;(IPC1-7):H03M13/12 主分类号 H03M13/41
代理机构 代理人
主权项
地址