CDR CIRCUIT, RECEIVING APPARATUS AND COMMUNICATION SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a CDR circuit, a receiving apparatus and a communication system that can implement high speed and resistance to jitter input and suppress the occurrence of signal errors by a simple circuit configuration.

SOLUTION: A CDR circuit 310 includes: a frequency divider 320 that includes delay elements 312-1 to 312-4 and extracts a clock when triggered by a data input with periodic signal transitions inserted; and latches 315-1 to 315-8 that latches the input data signal in synchronism with the clock extracted by the frequency divider.

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