发明名称 DUMMY-METAL-LAYOUT EVALUATING DEVICE AND DUMMY-METAL-LAYOUT EVALUATING METHOD
摘要 A dummy-mesh-information creating unit separates a group of dummy metal blocks that are arranged in a pattern regularly staggered with respect to a direction of a wire object into meshes so that each mesh has the same layout of dummy metal blocks. An overlap determining unit determines whether a dummy metal block within a dummy mesh overlaps with the wire object. A dummy-information calculating unit calculates dummy information after any dummy metal block that is determined to be overlapped with the wire object is removed. An information integrating unit integrates the dummy information with information about the wire object, thereby generating a dummy-fill circuit layout. An evaluating unit evaluates whether the dummy-fill circuit layout satisfies the design criteria.
申请公布号 US2012047472(A1) 申请公布日期 2012.02.23
申请号 US201113112192 申请日期 2011.05.20
申请人 FUKUDA DAISUKE;FUJITSU LIMITED 发明人 FUKUDA DAISUKE
分类号 G06F17/50 主分类号 G06F17/50
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