发明名称 |
Computer system with double width data bus |
摘要 |
A computer system is described with a 32 bit arithmetic and logic unit which is coupled to a 64 bit data bus. A number of general purpose registers are provided which have 32 bits each and which are organized in two groups. Two 32 bit data words which are present on the data bus can be transmitted and stored in the two groups of the general purpose registers. From there, the two data words can be transmitted via two operand registers to the arithmetic and logic unit. Several further lines are provided for bypassing the general purpose registers and/or the arithmetic and logic unit, if desired. Due to the fact that two data words can always be transmitted, the performance of the computer system is enhanced.
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申请公布号 |
US5754875(A) |
申请公布日期 |
1998.05.19 |
申请号 |
US19960588694 |
申请日期 |
1996.01.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GETZLAFF, KLAUS JOERG;HAJDU, JOHANN;HALLER, WILHELM ERNST;WITHELM, BIRGIT |
分类号 |
G06F13/36;G06F9/30;(IPC1-7):G06F3/14 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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