发明名称 Match line control circuit for content addressable memory
摘要 A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.
申请公布号 AU2718600(A) 申请公布日期 2000.07.24
申请号 AU20000027186 申请日期 2000.01.04
申请人 NETLOGIC MICROSYSTEMS, INC. 发明人 BINDIGANAVALE S. NATARAJ
分类号 G06F7/02;G11C15/04 主分类号 G06F7/02
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