Specifying and validating untimed nets

摘要

In accordance with an aspect of the present invention, specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physical Design by correlating latches and chip-level nets. This allows the testing process to become closed-loop. Design and simulation time is also greatly reduced due to the accessibility of RTL design.