发明名称
摘要 <P>PROBLEM TO BE SOLVED: To provide a video signal processor which can enhance stability of clock recovery. <P>SOLUTION: A receive buffer 1 stores received TS packets. A GAP restore section 2 restores time interval between time points when the TS packets stored in a receive buffer means are transferred. A control section 3 calculates the interval between time points when the TS packets stored in the receive buffer 1 are transferred, from a PCR value included in the TS packet and the number of TS packets included between the PCRs, and controls transfer of TS packets at the GAP restore section 2. Consequently, transfer rate of TS packets can be made constant substantially, and stability of clock recovery can be enhanced. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP4874272(B2) 申请公布日期 2012.02.15
申请号 JP20080011383 申请日期 2008.01.22
申请人 发明人
分类号 H04N7/173;H04L7/00;H04L12/70;H04L12/853;H04L12/885;H04N19/00;H04N19/196;H04N19/423;H04N19/44;H04N19/70;H04N19/80;H04N21/426;H04N21/438 主分类号 H04N7/173
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