| 摘要 |
A digital PLL circuit includes: an oscillation circuit, wherein an oscillation frequency is controlled by changing the number of capacitance elements to be connected in parallel to an inductance element; and a phase comparator part configured to perform a digital phase comparison of a reference clock and a delayed clock thereof, with an oscillation circuit output; and based on the comparison result, to control the number of the capacitance elements so as to bring the phase of the oscillation circuit output closer to the reference clock phase, wherein the capacitance element includes: a coarse adjustment capacitor configured to have a predetermined capacitance; and fine adjustment capacitors configured to have a capacitance of 1/n of that of the coarse adjustment capacitor, wherein a predetermined number of the fine adjustment capacitors function as one coarse adjustment capacitor at the time of coarse adjustment. |
