发明名称 REDUCTION OF INRUSH CURRENT DUE TO VOLTAGE SAGS WITH IMEPDANCE REMOVAL TIMING CIRCUIT
摘要 Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.
申请公布号 US2012032653(A1) 申请公布日期 2012.02.09
申请号 US201113274513 申请日期 2011.10.17
申请人 GEORGIA TECH RESEARCH CORPORATION 发明人 DIVAN DEEPAKRAJ
分类号 G05F1/00 主分类号 G05F1/00
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