发明名称 MEMORY MODULE AND LAYOUT METHOD THEREFOR
摘要 The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
申请公布号 US2012026772(A1) 申请公布日期 2012.02.02
申请号 US201113270587 申请日期 2011.10.11
申请人 HARASHIMA SHIRO;TSUKADA WATARU;ELPIDA MEMORY, INC. 发明人 HARASHIMA SHIRO;TSUKADA WATARU
分类号 G11C5/02 主分类号 G11C5/02
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