发明名称 |
Processor for executing an AES-type algorithm |
摘要 |
A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.
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申请公布号 |
US8102997(B2) |
申请公布日期 |
2012.01.24 |
申请号 |
US20040547195 |
申请日期 |
2004.03.29 |
申请人 |
TEGLIA YANNICK;ROMAIN FABRICE;LIARDET PIERRE-YVAN;FRAGNETO PASQUALINA;SOZZANI FABIO;BERTONI GUIDO;STMICROELECTRONICS S.A.;STMICROELECTRONICS S.R.L. |
发明人 |
TEGLIA YANNICK;ROMAIN FABRICE;LIARDET PIERRE-YVAN;FRAGNETO PASQUALINA;SOZZANI FABIO;BERTONI GUIDO |
分类号 |
H04L9/28;H04K1/00;H04L9/06 |
主分类号 |
H04L9/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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