| 摘要 |
The time compression processor coding methodology gives rise to an exceedingly fast clutter covariance processor compressor (CCPC). The CCPC includes a look up memory containing a very small number of predicted clutter covariances (PCCs) that are suitably designed off-line (e.g., in advance) using a discrete number of clutter to noise ratios (CNRs) and shifted antenna patterns (SAPs), where the SAPs are mathematical computational artifices not physically implemented. The on-line selection of the best PCC is achieved by investigating for each case, e.g., each range bin, the actual CNR, as well as the clutter cell centroid (CCC), which conveys information about the best SAP to select. The advanced CCPC is a ‘lossy’ processor coder that inherently arises from a novel practical and theoretical foundation for signal processing, namely, processor coding, that is the time compression signal processing dual of space compression source coding. |
