| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase locked loop, which can reduce a locking time of the phase locked loop and constantly has a short locking time, especially when a target value(a target frequency of an output clock) changes, and operation method of the same. <P>SOLUTION: The phase locked loop includes a phase comparison part 310 which compares a phase of an input clock CLK_IN and a phase of a feedback clock CLK_FB, a control part 330 which generates a frequency control signal DCO_CONTROL_SIGNALS according to comparison results UP, DN by the phase comparison part 310, an oscillator part 340 which generates an output clock CLK_OUT in response to the frequency control signal DCO_CONTROL_SIGNALS, and an initial value provision part 350 which detects a frequency of the input clock CLK_IN and provides an initial value INIT_VALUE according to a detection result to the control part 330. <P>COPYRIGHT: (C)2012,JPO&INPIT |
