SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THEM

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device comprising a plurality of core chips and an interface chip, which allows reduction in the minimum issue interval for the refresh command.

SOLUTION: In response to a refresh command REF and an address information SIDADD, a refresh control signal REFb and the address information SIDADD are supplied in common to CC0 to CC7. Each of the core chips CC0 to CC7 includes: a layer address comparison circuit 47 for determining whether the address information SIDADD specifies its own core chip; and a refresh control circuit 200 for refreshing its own memory cell on the basis of the refresh control signal REFb when the address information SIDADD specifies its own core chip. Thus, the memory capacity of a chip to be refreshed by one refresh command is reduced, allowing reduction in the minimum issue interval for the refresh command.

COPYRIGHT: (C)2012,JPO&INPIT