发明名称 Integrated circuit with through-die via interface for die stacking and cross-track routing
摘要 An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.
申请公布号 US8089299(B1) 申请公布日期 2012.01.03
申请号 US20090436918 申请日期 2009.05.07
申请人 RAHMAN ARIFUR;NEW BERNARD J.;XILINX, INC. 发明人 RAHMAN ARIFUR;NEW BERNARD J.
分类号 H03K19/177 主分类号 H03K19/177
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