发明名称 |
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME |
摘要 |
A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.
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申请公布号 |
US2011316141(A1) |
申请公布日期 |
2011.12.29 |
申请号 |
US20100822601 |
申请日期 |
2010.06.24 |
申请人 |
SAE MAGNETICS(H.K) LTD.;HEADWAY TECHNOLOGIES, INC. |
发明人 |
SASAKI YOSHITAKA;ITO HIROYUKI;IKEJIMA HIROSHI;IIJIMA ATSUSHI |
分类号 |
H01L23/485;H01L21/60;H01L21/822 |
主分类号 |
H01L23/485 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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