发明名称
摘要 In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage generating circuit generates a word line write voltage in a first write operation or a second write operation on the basis of the initial value and correction value of the write voltage stored in the storage section.
申请公布号 JP4846314(B2) 申请公布日期 2011.12.28
申请号 JP20050275998 申请日期 2005.09.22
申请人 发明人
分类号 G11C16/02;G11C16/04;G11C16/06 主分类号 G11C16/02
代理机构 代理人
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