| 摘要 |
A one cycle power factor correction converter circuit comprising a switch for controlling a DC output voltage of the converter circuit, the switch being switched by a drive signal having a frequency determined by a clock signal; the converter circuit being provided with a DC input voltage and producing the DC output voltage, the DC input voltage being rectified from an AC input; a controller circuit for controlling an on-time or off-time of the switch to set the output voltage and to achieve power factor correction at the AC input; the controller circuit comprising an error amplifier receiving a feedback voltage from the output of the converter circuit and a reference voltage and producing an error signal; a ramp generator receiving the error signal and generating a first ramp signal by integrating a signal related to the error signal; a pulse width modulation circuit receiving the first ramp signal and a signal related to the error signal and producing a pulse width modulated signal by comparing the first ramp signal and the signal related to the error signal; the pulse width modulated signal determining the on-time or off-time of the switch to control the output voltage with power factor correction; further comprising a circuit for terminating the first ramp signal when a predetermined inequality exists between the first ramp signal and a reference signal and for developing the clock signal from the first ramp signal. |
