发明名称 Indexed table circuit having reduced aliasing
摘要 In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.
申请公布号 US8086831(B2) 申请公布日期 2011.12.27
申请号 US20080024241 申请日期 2008.02.01
申请人 CHEN LEI;ZHANG LIXIN;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHEN LEI;ZHANG LIXIN
分类号 G06F9/35;G06F9/355 主分类号 G06F9/35
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