| 摘要 |
PURPOSE: A delay locked loop including loop bandwidth dependency on a phase error is provided to quickly reduce a large phase error by increasing a loop bandwidth. CONSTITUTION: A phase detector includes a first input terminal which receives a clock signal. A loop filter has an input terminal connected to the output terminal of the phase detector. A data input and output circuit(212,222) includes a delay locked loop(216,226) including the delay line. A delay line has an output terminal and a control input terminal which receives the output of the loop filter. A control circuit determines a phase error range between the received clock signal and the retimed clock signal and sets the depth of the loop filter by using the determined phase error range.
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