| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a cache memory device capable of reducing deterioration of performance and reducing increase of power consumption. <P>SOLUTION: A cache memory device 100 connected to a processor section 200 which executes plural programs while switching the programs, comprises: cache memory 110 of a set associative system having plural ways including a tag storing section and a data storing section; a way prediction section 120 that predicts a way to be hit among the plural ways; and a clock control section 113. When the processor section 200 reads a first memory access command, the clock control section 113 supplies the clocks to only the data storing section of the way predicted by the way prediction section 120; and when the processor section 200 reads a second memory access command, the clock control section 113 supplies the clocks to a predetermined data storing section regardless of the prediction result by the way prediction section 120. <P>COPYRIGHT: (C)2012,JPO&INPIT |
