| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve shortening of the lockup time and reduction of the reference leakage in a balanced manner. <P>SOLUTION: A PLL circuit has: an analog/digital conversion circuit (106) that outputs a digital signal (ADCO) obtained by carrying out analog/digital conversion of a control voltage VCONT from a voltage control oscillator (104); a lock detector (201) that outputs a lock detection signal (S201) when the lock of a reference clock signal (FREF) and a feedback clock signal (FDIV) is detected; a holding part(107) that holds the digital signal at the time of locking, which is inputted from the analog/digital conversion circuit, when the lock detection signal is inputted from the lock detector; and a charge pump controller (108) that generates a charge pump current amount control signal (CPCONT) to reduce the current amount of a charge pump current in a stepwise fashion, based on a comparison result of the digital signal at the time of locking, which is held by the holding part, and a digital signal outputted from the analog/digital conversion circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT |
