| 摘要 |
<P>PROBLEM TO BE SOLVED: To implement a cache coherence protocol for a processor system including persistent memory in at least part of main memory thereof. <P>SOLUTION: A processing system 100 comprises a memory controller 115 having at least one first interface for a main memory 120 and at least one second interface for two or more processing entities 110. The memory controller 115 allows the processing entities 110 to access the main memory 120 in accordance with a cache coherence protocol, and at least part of the main memory 120 includes persistent memory. The cache coherence protocol 140 includes an in-process state 142 so as to enable accommodation of the persistent memory. <P>COPYRIGHT: (C)2012,JPO&INPIT |
