| 摘要 |
<p>PURPOSE: The overlay vernier of a semiconductor device and a manufacturing method thereof are provided to measure the aligned state of the upper layer and the lower layer of a wafer using the through silicon via on the backside of the wafer. CONSTITUTION: Through silicon via(110) is formed in a semiconductor substrate. The through silicon via is exposed by grinding the back side of the semiconductor substrate. An insulation layer is formed on the front part including exposed through silicon via. An insulation layer pattern(170), in which the insulation layer is etched using a child vernier mask as an etching mask and exposes the through silicon via, is formed. The through silicon via includes a circular, a rectangular, or a square shape.</p> |
