发明名称 |
SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE |
摘要 |
In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.
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申请公布号 |
US2011305057(A1) |
申请公布日期 |
2011.12.15 |
申请号 |
US201113160198 |
申请日期 |
2011.06.14 |
申请人 |
HAYASHI JUNICHI;IDE AKIRA;ELPIDA MEMORY, INC. |
发明人 |
HAYASHI JUNICHI;IDE AKIRA |
分类号 |
G11C7/00;G11C5/02 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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