发明名称 |
SEMICONDUCTOR DEVICE, AND DESIGN METHOD, DESIGN TOOL, AND FAULT DETECTION METHOD OF SEMICONDUCTOR DEVICE |
摘要 |
A bridging fault which has occurred between clock signal lines in a semiconductor device can be easily detected. A semiconductor device having a plurality of hold circuits and configured such that a scan test can be performed includes a first and a second clock signal lines supplied with normal operational clock signals having at least either frequencies or phases different from each other during normal operation, and a test clock signal controller which switches, during a test, between a state in which a first test clock signal, which is the same as that supplied to the first clock signal line, is supplied to the second clock signal line, and a state in which a second test clock signal, which is inverted or phase-shifted relative to the first test clock signal, is supplied to the second clock signal line. |
申请公布号 |
US2011307752(A1) |
申请公布日期 |
2011.12.15 |
申请号 |
US201113218207 |
申请日期 |
2011.08.25 |
申请人 |
FUJIL NAOHIRO;DAIO KINYA;YOSHIMURA SHINICHI;PANASONIC CORPORATION |
发明人 |
FUJIL NAOHIRO;DAIO KINYA;YOSHIMURA SHINICHI |
分类号 |
G01R31/3177;G06F11/25;G06F17/50 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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