发明名称 |
DSP execution unit for efficient alternate modes of operation |
摘要 |
<p>A system comprising: a bus; and a digital signal processor comprising: a multiplier having a first structure and a second structure, the first structure processing data up to n-bits and the second structure processing data up to (n/2)-bits; and a data size selector which configures the multiplier into the first structure of a single n-bit multiplier when the data is greater than (n/2)-bits and configures the multiplier into the second structure of two (n/2)-bit multipliers when the data is (n/2)-bits or less.</p> |
申请公布号 |
EP2296093(A3) |
申请公布日期 |
2011.12.14 |
申请号 |
EP20100184777 |
申请日期 |
2001.04.02 |
申请人 |
ANALOG DEVICES, INC. |
发明人 |
ALDRICH, BRADLEY;FRIDMAN, JOSE;MEYER, PAUL |
分类号 |
G06F9/302;G06F7/50;G06F7/52;G06F7/57;G06F15/78 |
主分类号 |
G06F9/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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