| 摘要 |
PURPOSE: A duty correcting circuit including a duty detector, a delay locked loop circuit including the same, and a duty correcting method thereof are provided to correct a duty by controlling the delay time of a sampling clock signal based on the logic state of sampled data. CONSTITUTION: A duty cycle correcting unit(110) generates an output clock signal by correcting a duty cycle of an input clock signal. A duty detector(120) generates a sampling clock signal by controlling the delay time of an output clock signal, samples the output clock signal in response to the sampling clock signal, and generates the first sample data and the second sample data. The duty detector detects the duty of the output clock signal based on the logic states of the first and second sample data and generates a duty up signal and a duty down signal. A duty correction code generator(150) generates a duty correction code in response to the duty up signal and the duty down signal. |
