| 摘要 |
PURPOSE: A frequency-phase-locked loop with a self-noise suppressing voltage controlled oscillator is provided to drastically reduce the capacitance of a capacitor of a loop filter, thereby easily forming a PLL in one chip. CONSTITUTION: A phase-frequency detector(100) compares the phase of an input clock with the phase of a feedback flock to output an up-signal or a down-signal. The input clock is assigned to a frequency-phase-locked loop. A charge pump(200) outputs a current in proportional to the up-signal and the down-signal. A loop filter(300) smoothes a current outputted from the charge pump to output a voltage. A voltage controlled oscillator(400) outputs a frequency based on a voltage outputted from the loop filter. A frequency demultiplier(500) demultiplies an output frequency of the voltage controlled oscillator to feed the demultiplied frequency to the phase-frequency detector. A frequency-voltage transformer(600) generates a voltage corresponding to the output frequency of the voltage controlled oscillator. The frequency-voltage transformer feeds the generated voltage back to the voltage controlled oscillator to cancel noise of the voltage controlled oscillator. |
