| 摘要 |
In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the frames in general and commands for second slots of at least some frames immediately preceding frequency mismatch bubbles occurring when the frames are at a second frequency. The clock gearing logic is to provide the signals having the first frequency from the scheduler to the transmitters at the second frequency. Other embodiments are described. |
