| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve timing convergence in a layout design of a semiconductor integrated circuit. <P>SOLUTION: In the layout method for a semiconductor integrated circuit according to the present invention, M (M is an integer ≤2 and ≥N (N is an integer ≤3)) sequential circuits are selected out of N sequential circuits which are installed on the semiconductor integrated circuit and whose clocks are distributed from the same clock root, and the selected M sequential circuits are replaced with one multi-data input/output sequential circuit having M input and output terminals and one clock terminal receiving clocks distributed from the clock root. <P>COPYRIGHT: (C)2012,JPO&INPIT |
