发明名称 |
MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION |
摘要 |
An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short- circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model. |
申请公布号 |
WO2011116056(A3) |
申请公布日期 |
2011.11.24 |
申请号 |
WO2011US28613 |
申请日期 |
2011.03.16 |
申请人 |
SYNOPSYS, INC.;TANG, QIAN-YING;CHEN, QIANG;TIRUMALA, SRIDHAR |
发明人 |
TANG, QIAN-YING;CHEN, QIANG;TIRUMALA, SRIDHAR |
分类号 |
G06F19/00;G06F9/44;G06F17/50;G11C29/54 |
主分类号 |
G06F19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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