发明名称 Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program
摘要 A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.
申请公布号 US8065645(B2) 申请公布日期 2011.11.22
申请号 US20070754410 申请日期 2007.05.29
申请人 INUI SHIGETO;HAGIHARA YASUHIKO;NEC CORPORATION 发明人 INUI SHIGETO;HAGIHARA YASUHIKO
分类号 G06F9/455;G06F17/50;H01L21/82;H01L21/822;H01L27/04;H03K3/012;H03K3/037;H03K3/12;H03K17/693;H03K19/00 主分类号 G06F9/455
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